This invention relates generally to digital logic circuitry and, more particularly, to a current mode arithmetic logic circuit with parity prediction and checking.
Various arithmetic logic units are known in the prior art. A 4-bit arithmetic logic unit with parity and a 5-bit arithmetic logic unit with parity are disclosed in the above-identified Ser. Nos. 756,456 and 756,458. The 4-bit arithmetic logic unit with parity disclosed in Ser. No. 756,458 is capable of performing parity prediction, parity checking, and carry checking operations on a 4-bit plus parity byte. The current mode arithmetic logic circuit with parity prediction and checking of the present invention provides, in addition to 16 basic arithmetic and 16 logic functions, necessary and useful parity prediction, parity checking, and carry checking operations on an n-bit plus parity byte. The particular form of implementation of the present invention depends upon the byte length n. The present invention has significant value in the early detection of errors generated within the arithmetic logic circuit or generated during the transmission of the binary data to such circuit, resulting in an overall savings of processing time. In addition, the present invention offers greater flexibility regarding the byte length of the binary data which may be operated on than the 4-bit arithmetic logic unit disclosed in Ser. No. 756,458 mentioned above.